1. Field of the Invention
The present invention relates generally to methods for approximating cycle times within fabrication facilities. More particularly, the present invention relates to methods for accurately and efficiently approximating cycle times within fabrication facilities.
2. Description of the Related Art
Microelectronic fabrications are formed from microelectronic substrates over which are formed patterned microelectronic conductor layers which are separated by microelectronic dielectric layers.
As is understood by a person skilled in the art, microelectronic fabrications, and in particular semiconductor integrated circuit microelectronic fabrications, are typically fabricated within microelectronic fabrication facilities while employing intricate multi-step microelectronic fabrication processes which employ a multiplicity of microelectronic fabrication tools within a generally distributed and repetitive microelectronic fabrication process to provide microelectronic fabrications which are generally fabricated with patterned microelectronic conductor layers which are horizontally and vertically separated by microelectronic dielectric layers.
Significant to the fabrication of microelectronic fabrications within microelectronic fabrication facilities is the approximation of cycle times for individual work in process (WIP) workload lots released for fabrication within microelectronic fabrication facilities. Approximation of cycle times for individual work in process (WIP) workload lots is of considerable importance when fabricating microelectronic fabrications within microelectronic fabrication facilities insofar as accurate cycle time approximations provide for enhanced microelectronic fabrication order confirmation accuracy and enhanced microelectronic fabrication facility operational control when fabricating microelectronic fabrications within microelectronic fabrication facilities.
It is thus desirable in the art of microelectronic fabrication to provide methods for accurately and efficiently approximating cycle time when fabricating microelectronic fabrications within microelectronic fabrication facilities.
It is towards the foregoing object that the present invention is directed.
Various methods have been disclosed within various fabrication arts for monitoring and controlling fabrication facilities when fabricating products therein.
Included among the methods, but not limited among the methods, are methods disclosed within: (1) Wang, in U.S. Pat. No. 5,825,650 (a method for dynamically approximating a standard cycle time for an individual process stage when fabricating a semiconductor integrated circuit microelectronic fabrication lot within a semiconductor integrated circuit microelectronic fabrication facility, by use of a regressive analysis directed towards past cycle time measurements in conjunction with fabrication facility equipment utilization rates for prior semiconductor integrated circuit microelectronic fabrication lots fabricated within the semiconductor integrated circuit microelectronic fabrication facility); (2) Lin et al., in U.S. Pat. No. 5,880,960 (a method for enhancing work in process (WIP) workload queue balance within a fabrication facility, such as a semiconductor integrated circuit microelectronic fabrication facility, by defining in a first instance a daily standard move quantity of product which is desired to be produced from the fabrication facility); and (3) Rothschild et al., in U.S. Pat. No. 5,966,694 (a method for overall cycle time costing within a fabrication facility, by determining, analyzing and coalescing fabrication facility data for individual fabrication cells within the fabrication facility).
Desirable in the art of microelectronic fabrication are additional methods which may be employed in the art of microelectronic fabrication for approximating, with enhanced accuracy and efficiency, cycle times for fabricating microelectronic fabrication work in process (WIP) workload lots within microelectronic fabrication facilities.
It is towards the foregoing object that the present invention is directed.
A first object of the present invention is to provide a method for approximating a cycle time for fabricating a microelectronic fabrication work in process (WIP) lot within a microelectronic fabrication facility.
A second object of the present invention is to provide a method in accord with the first object of the present invention, wherein the cycle time is accurately and efficiently approximated.
A third object of the present invention is to provide a method in accord with the first object of the present invention and the second object of the present invention, wherein the method is readily commercially implemented.
In accord with the objects of the present invention, there is provided by the present invention a method for approximating a cycle time for fabricating a microelectronic fabrication within a microelectronic fabrication facility.
To practice the method of the present invention, there is first provided a microelectronic fabrication facility for fabricating a microelectronic fabrication product having a minimum of one layer. There is then determined from historic data for fabricating the microelectronic fabrication product within the microelectronic fabrication facility a positive value of h such as to minimize the summation:
xcexa3i(mxe2x88x92 greater than n)(Wixe2x88x92(h*Ti))2
where: (1) Wi is the work in process (WIP) quantity of the microelectronic fabrication product on day i; (2) Ti is the cycle time per photo layer of the microelectronic fabrication product on day i; and (3) m and n bound an arbitrarily chosen historic date range. There is then approximated a future work in process (WIP) quantity of the microelectronic fabrication product for a future start date within the microelectronic fabrication facility. Finally, there is then approximated a cycle time for the future work in process (WIP) quantity of the microelectronic fabrication product within the microelectronic fabrication facility using the equation:
xe2x80x83CTf=Wf*(1/h)*L
where: (1) CTf is the cycle time approximated for the future work in process (WIP) quantity of the microelectronic fabrication product; (2) Wf is the approximated future work in process (WIP) quantity of the microelectronic fabrication product; and (3) L is the number of photo layers of the microelectronic fabrication product.
The present invention provides a method for accurately and efficiently determining a cycle time for fabricating a microelectronic fabrication within a microelectronic fabrication facility.
The method of the present invention realizes the foregoing object by employing a mathematical algorithm for approximating the cycle time for fabricating the microelectronic fabrication within the microelectronic fabrication facility, wherein the mathematical algorithm operates upon: (1) an historic work in process (WIP) workload loading of the microelectronic fabrication product within the microelectronic fabrication facility; in conjunction with (2) an historic cycle time for the historic work in process (WIP) workload loading of the microelectronic fabrication product within the microelectronic fabrication facility.
The method of the present invention is readily commercially implemented.
The present invention employs data accumulation methods and data reduction methods as are otherwise readily adaptable to the art of microelectronic fabrication, but employed within the context of a specific mathematical algorithm to provide a method in accord with the present invention.
Since it is thus a specific mathematical algorithm which provides at least in part the present invention, rather than the existence of methods and materials which provides the present invention, the method of the present invention is readily commercially implemented.